1. Field of the Invention
The present invention relates to synchronization detection using multiphase clock signals.
2. Description of Related Art
Currently, control operation using a synchronous signal is performed in various electrical devices. For example, the synchronous signal is used for control of print tone in laser beam printers, digital copiers, and the like. To achieve the control operation, there is employed a synchronization detection circuit for detecting the input timing of the synchronous signal using multiphase clock signals. The synchronization detection circuit is basically configured to compare a pulse edge of the synchronous signal with a pulse edge of each of clock signals constituting the multiphase clock signals, thereby specifying a clock signal having a pulse edge closest to that of the synchronous signal from among the multiphase clock signals.
A technology relating to the above-mentioned synchronization detection circuit is disclosed in Japanese Unexamined Patent Application Publication Nos. 2006-20109 and 2008-55750. In the configuration disclosed in Japanese Unexamined Patent Application Publication No. 2006-20109, an intermediate clock signal is generated by a phase locked loop circuit, and phase interpolation processing is then performed on the intermediate clock signal, to thereby generate multiphase clock signals based on the reference clock signal. In this manner, the multiphase clock signals are generated using the phase locked loop circuit as well as a phase interpolation circuit, thereby preventing a reduction in processing speed which is caused when only the phase locked loop circuit is used, and also prevent a reduction in detection accuracy which is caused when only the phase interpolation circuit is used.
In the configuration disclosed in Japanese Unexamined Patent Application Publication No. 2008-55750, a synchronous signal is compared with speeded-up multiphase clock signals having a frequency which is k times as high as that of the reference clock signal. Then, the number of time that a representative clock signal selected from the speeded-up multiphase clock signals, e.g., the head clock signal in the multiphase clock signals appeared is counted. By this counting, a cycle of the multiphase clock signals is specified. The speeded-up multiphase clock signals have a phase shift interval smaller than that obtained before speeding up the multiphase clock signals, and thus have a higher resolution. Accordingly, the use of the speeded-up multiphase clock signals makes it possible to perform the synchronization detection with high accuracy.